1. Field of the Invention
The invention relates to the field of memory arrays. More particularly, the invention relates to a process for efficiently evaluating the operability of memory chips.
2. Description of the Related Technology
Substantially all modern electronic computers rely on semiconductor memory or memory chips to store data for processing by a central processing unit (CPU). Such computers employing memory chips vary from simple computers, such as those contained in telephone answering machines, to highly complex supercomputers employed for complicated scientific projects. The operability and functionality of these memory chips must be guaranteed after being manufactured. One or more defective memory locations in a memory of a computer used to perform scientific calculations may cause substantial problems.
Although current manufacturing techniques have substantially reduced the number of defective memory locations, excessive numbers of defective memory locations are still produced during the fabrication of computer memory. Those defective memory locations can be caused by an error in any of numerous steps taken during the manufacture of the memory chips such as is seen in semiconductor crystalinity defects and electrical connector discontinuities. Although memory chips with such defective memory locations typically represent a small portion (less than 1%) of the total number of memory chips produced, the actual number of such defective memory chips is substantial since computer manufacturers create many millions of memory chips each year.
Each memory chip includes a memory array, which is the area of the memory chip that stores bits of information. The array consists of rows and columns, with a cell at each intersection to store a bit. Manufacturers often use diagnostic programs to test each memory array before the array is shipped to the customers. These programs test the operability of each memory chip by writing a value into each memory cell and then reading the contents of that cell. If the value read from the memory cell is the same as that which was written into the memory cell, that particular memory cell is presumed to be functional.
FIGS. 1a and 1b are block diagrams illustrating the internals of some conventional memory chips. FIG. 1a illustrates a 4 Megabyte (M).times.4 memory chip 100. The memory chip 100 has four memory arrays 102-108, each holding 4M of storage cells. The memory arrays 102-108 have 2048 rows and 2048 columns of memory cells. Each of four pins 110.varies.116 allows access to one of the memory arrays 102-108. FIG. 1b illustrates a 2M.times.8 memory chip 118. The memory chip 118 has 8 memory arrays 120-126. The memory arrays 120-126 each hold 2M of memory. Each of the memory arrays 120-126 contains 1024 rows and 2048 columns of memory cells.
FIG. 2 is a diagram illustrating two traditional memory chip handlers 200. Since thousands of memory chips need to be tested, memory chip handlers have been created to manipulate the memory chips for testing. An example of a commercial handler is the Atrium M4300 by Simtek. The handlers 200 carry a plurality of memory chips 202. Each of the handlers 200 can typically hold up to 32 memory chips at one time 202.
The handlers 200 are both connected to a testing computer 204 which runs a series of diagnostic tests on the memory chips 202. An example of a testing computer 204 is the Mongoose J994 manufactured by Teradyne. The testing computer 204 performs such tests as applying a range of voltages to the memory chips 202 as well as performing several types of memory diagnostic tests. However, one problem with the current testing computers is that they run the diagnostic tests on all of the memory in a memory array even upon the identification of a malfunctioning memory cell. If the memory chip 202 has a number of bad or marginal cells, time is wasted testing the entire memory array since the identification of a single malfunctioning cell often makes the memory chip not salable.
Additionally, such a testing process has been found to be very time consuming, especially in the retesting of previously identified bad memory chips. Bad memory chips 202 are often re-tested to re-evaluate whether a memory chip 202 was mis-identified. Sometimes, memory chips 202 appear to be malfunctioning due to faulty contacts with the handlers 200. Thus, a second evaluation of the memory chips 202 that failed the first testing may reveal that some of the memory chips 202 are actually operational. However, even though most of the cells are bad, traditional testing methodologies evaluate all of the memory cells on the memory chip before proceeding to the next chip. This thorough evaluation of all of the memory cells in the memory chip, after identifying some of the cells on the memory chip as malfunctioning, wastes time.
Therefore, memory chip manufacturers are in need of a testing process and system which would test memory chips in an efficient and cost effective manner.